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2-34 Service Guide
Table 2-4 M7101 Pin Descriptions (Continued)
Name No. Type Description
Power Pins
VDD5 x 3 11,59,76 P 5V VDD input
VDD3 x 2 26,100 P 3.3V VDD input
VDDS x 1 46 P 5V Suspend VDD input. This pin supplies to RI, RTC, HOTKEYJ,
COVSW, SUSTATE, PWGD, SUSRSTJ pad.
VSS x 5 1,19,38,
63,90
P VSS Ground.
2.4.4 Different Pin definition setting
• SLED, CCFT, DISPLAY, SPKCTL, SQWO and GPIOC2 pins are all internal pull high 50K
ohms. The blank part of following table means keeping the original pin definition.
• When SLED default is pulled high, the chip will be in normal mode.
• When SLED is pulled low by 4.7K resistor, the chip will be in test mode.
• When GPIOC2 pull low, the PCI ports are 0078/007A and offset 0F6h D15 will be set, otherwise,
0178/017A.
Table 2-5 M7101 Different Pin Definition Setting
Original pin
definition
CCFT
pull low 4.7K
DISPLAY
pull low 4.7K
SPKCTL
pull low 4.7K
SQWO
pull low 4.7K
offset 0F6h D1=1 offset 0F6h D2=1 offset 0F6h D3=1 offset 0F6h D4=1
GPIOA5 GPIOWB
GPIOA4 GPIORBJ
GPIOA1 GPIOWA
GPIOA0 GPIORAJ
GPIOB7 STPCLKJ
GPIOB6 AMSTATJ
GPIOB5 OUT_INIT
GPIOB4 OUT_INTR
GPIOB3 IN_BRDYJ
GPIOB2 IN_INIT
GPIOB1 IN_SMIJ
GPIOB0 IN_INTR
GPIOC2 BIOSA17
GPIOC1 BIOSA16
GPIOC0 ISA16