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ARM Instruction Reference
4-6 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
4.2 ARM memory access instructions
This section contains the following subsections:
• LDR and STR, words and unsigned bytes on page 4-7
Load register and store register, 32-bit word or 8-bit unsigned byte.
• LDR and STR, halfwords and signed bytes on page 4-12
Load register, signed 8-bit bytes and signed and unsigned 16-bit halfwords.
Store register, 16-bit halfwords.
• LDR and STR, doublewords on page 4-15
Load two consecutive registers and store two consecutive registers.
• LDM and STM on page 4-18
Load and store multiple registers.
• PLD on page 4-20
Cache preload.
• SWP on page 4-22
Swap data between registers and memory.
There is also an
LDR
pseudo-instruction (see LDR ARM pseudo-instruction on
page 4-82). This pseudo-instruction sometimes assembles to an
LDR
instruction, and
sometimes to a
MOV
or
MVN
instruction.