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ARM Instruction Reference
4-46 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
4.4.4 SMLAxy
Signed multiply-accumulate (16-bit by 16-bit, 32-bit accumulate).
Syntax
SMLA<x><y>{cond} Rd, Rm, Rs, Rn
where:
<x>
is either
B
or
T
.
B
means use the bottom end (bits [15:0]) of
Rm
,
T
means
use the top end (bits [31:16]) of
Rm
.
<y>
is either
B
or
T
.
B
means use the bottom end (bits [15:0]) of
Rs
,
T
means
use the top end (bits [31:16]) of
Rs
.
cond
is an optional condition code (see Conditional execution on page 4-4).
Rd
is the ARM register for the result.
Rm, Rs
are the ARM registers holding the values to be multiplied.
Rn
is the ARM register holding the value to be added.
r15 cannot be used for any of
Rd
,
Rm
,
Rs
, or
Rn
.
Any combination of
Rd
,
Rm
,
Rs
, and
Rn
can use the same registers.
Usage
The
SMLAxy
instruction multiplies the 16-bit signed integers from the selected halves of
Rm
and
Rs
, adds the 32-bit result to the 32-bit value in
Rn
, and places the result in
Rd
.
Condition flags
This instruction does not affect the N, Z, C, or V flags.
If overflow occurs in the accumulation, it sets the Q flag. To read the state of the Q flag,
use an
MRS
instruction (see MRS on page 4-73).
Note
This instruction never clears the Q flag. To clear the Q flag, use an
MSR
instruction (see
MSR on page 4-74).