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ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 5-23
5.3.1 AND, ORR, EOR, and BIC
Bitwise logical operations.
Syntax
op Rd, Rm
where:
op
is one of
AND
,
ORR
,
EOR
, or
BIC
.
Rd
is the destination register. It also contains the first operand.
Rd
must be in
the range
r0
-
r7
.
Rm
is the register containing the second operand.
Rm
must be in the range
r0
-
r7
.
Usage
These instructions perform a bitwise logical operation on the contents of
Rd
and
Rm
, and
place the result in
Rd
. The operations are as follows:
• the
AND
instruction performs a logical AND operation
• the
ORR
instruction performs a logical OR operation
• the
EOR
instruction performs a logical Exclusive OR operation
• the
BIC
instruction performs an
Rd
AND NOT
Rm
operation.
Condition flags
These instructions update the N and Z flags according to the result. The C and V flags
are not affected.
Architectures
These instructions are available in all T variants of the ARM architecture.
Example
AND r2,r4