Filter
Top Products
Vector Floating-point Programming
6-22 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
6.7.6 FDIV
Floating-point divide.
FDIV
can be scalar, vector, or mixed (see Vector and scalar
operations on page 6-7).
Syntax
FDIV<precision>{cond} Fd, Fn, Fm
where:
<precision>
must be either
S
for single-precision, or
D
for double-precision.
cond
is an optional condition code (see VFP and condition codes on page 6-8).
Fd
is the VFP register for the result.
Fn
is the VFP register holding the first operand.
Fm
is the VFP register holding the second operand.
The precision of
Fd
,
Fn
and
Fm
must match the precision specified in
<precision>
.
Usage
The
FDIV
instruction divides the value in
Fn
by the value in
Fm
and places the result in
Fd
.
Exceptions
FDIV
operations can produce Division by Zero, Invalid Operation, Overflow, Underflow,
or Inexact exceptions.
Examples
FDIVS s8, s0, s12
FDIVSNE s2, s27, s28
FDIVD d10, d2, d10