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SDM-SW8A Switch Closure Input Module
50% Duty Cycle - The "worst case" duty cycle measurement error for a 50%
duty cycle at a given input frequency is
±ERROR = Hz * 0.4
where ERROR = Actual Duty Cycle ±Measured Duty Cycle.
For example, a 50% duty cycle at 10 Hz could be measured as 46% to 54% in
the worst case.
Minimum/Maximum - The measurable minimum/maximum duty cycle is
defined by the 5 ms pulse width specification of the SW8A. For example, at a
10 Hz frequency, the minimum and maximum duty cycle that can be measured
is 5% and 95%, respectively (0.005/0.100 * 100). The "worst case" duty cycle
measurement error for the minimum/maximum measurable duty cycle is
±ERROR = Hz * 0.3
For example, the minimum measurable duty cycle for a 1 Hz signal is 0.5%.
The duty cycle measurement could range from 0.2% to 0.8%.
Signal Magnitude - The signal magnitude should range from 0 - 0.9 V low, to
4 - 5 V high, or the signal should be centered around 2.5 V with a minimum 8
V peak to peak magnitude. When the magnitude is 0 V to greater than 5 V, the
wave form begins to distort, resulting in less accurate duty cycle information.
9. Theory of Operation
The Switch Closure Input Module uses a 63705 microprocessor to sample the
8 ports and communicate with the datalogger. The processor is in a low power
"Wait" mode except when interrupted.
An internal timer interrupts the processor approximately every 2 milliseconds
to sample the input ports. At this time, for each port, the duty cycle
accumulator is updated, and the transition counter is incremented if the state
represents a positive transition from the previous state.
C3, driven high by the datalogger, also interrupts the SW8A. The SW8A
prepares to receive an 8 bit byte (consisting of address in the most significant
nibble and command in the least significant nibble with the least significant bit
always a 1) from the datalogger. The datalogger drives C2 as a clock line and
C1 as a serial data out line. The datalogger shifts out each bit (LSB first) on
the falling edge of the clock; the Switch Closure Module shifts in each bit on
the rising edge of the clock.
When all 8 bits are received by the SW8A, the SW8A is again interrupted by
its serial communication interface. If the address part of the byte received
equals the jumpered address, the SW8A executes the command part, providing
it is valid. For Function Options 1 and 2, the module receives another byte
containing Reps and Channel information from the datalogger. For a valid
address and command, the SW8A prepares to return a code byte as
acknowledgment to the datalogger. Except for the 21X, the datalogger
switches C1 to an input and after 2 milliseconds clocks back the code byte
from the SW8A. If the code byte is correct, the datalogger knows the
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