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Schematic Diagrams
B - 4 Socket 478 & ITP 2 of 2 (71-D40U0-D03)
B.Schematic Diagrams
Socket 478 & ITP 2 of 2
VCC_CORE
VCC_CORE
VCC_CORE
+3V
+3V VDD3
VCC_CORE
VCC_CORE
VCC_CORE
VCCVID
INTR15
NMI15
DEFER# 5
HTRDY# 5
BPRI# 5
INIT# 15
STPCLK# 15
CPUPWRGD 5
CPURST# 5
CPUSLP# 15
SMI# 15
IGNNE# 15
A20M# 15
FERR# 15
BNR# 5
BREQ0# 5
DBSY# 5
DRDY# 5
HLOCK# 5
HITM# 5
HIT# 5
HCLK-CPU#4
HCLK-CPU4
BSEL0 4
ADS# 5
HASTB#05
HDSTBN#05
HDSTBN#15
HDSTBN#25
HDSTBN#35
HDSTBP#05
HDSTBP#15
HDSTBP#25
HDSTBP#35
TMP_SMDATA24
TMP_SMCLK24
HASTB#15
DBI#[0..3]5
HBPM0#2
HBPM1#2
HBPRM5#2
HBPRM4#2
BSEL1 4
ALERT#27
VSS_SENSE36
VCC_SENSE36
SENSE_VCC_REST24
ITP_STPWR
HBPRM4#
HBPM0#
HBPM1#
FERR#
BREQ0#
PROCHOT#
CPUPWRGD
THERMTRIP#
A20M#
STPCLK#
CPUSLP#
SMI#
INIT#
IGNNE#
INTR
NMI
CPURST#
HTDO
IERR
HCLK-CPU
HCLK-CPU#
HBPRM5#
SENSE_VCC
DBRESET
HCLK-ITP0
HCLK-ITP0#
HTRST#
HTDI
HTCK
HTMSTHERMTRIP#
HTRST#
DBI#0
HCLK-CPU#
HTDO
INIT#
STPCLK#
HDSTBP#1
DBI#3
HCLK-CPU
HDSTBN#1
SMI#
DEFER#
BNR#
DRDY#
IGNNE#
HTDI
HCLK-ITP0
VSS_SENSE
CPUPWRGD
THERMDC
A20M#
HDSTBP#0
HASTB#1
DBI#[0..3]
CPUSLP#
HDSTBN#2
CPUGTLVREFA
THERMDA
ADS#
BPRI#
FERR#
DBI#2
CPURST#
HTMS
HTCK
HITM#
HLOCK#
NMI
HASTB#0
INTR
HCLK-ITP0#
CPUGTLVREFB
HIT#
HTRDY#
DBSY#
HDSTBN#0
HDSTBP#2
THERMDC
HDSTBP#3
DBRESET
THERMDA
DBI#1
VCC_SENSE
IERR
PROCHOT#
BREQ0#
HDSTBN#3
ALERT#
SENSE_VCC_REST
R404
4.7K
R349 51
R324
49.9_1%
C512
0.1UF
C339
0.1UF
R323
100_1%
C492
1UF
R263 51_1%
C75
2200P
C74
0.1UF
R110
2.2K
R348 51
RP34 4P2R-0(R)
1
23
4
R307 51_1%
R83
39
T
R424
56_1%
R69
150
C775
0.1UF
12
R345
56_1%
R102 56_1%
R405 200
C338
220P
Q44
DTA114EUA(R)
C
E
B
C377
10U(0805)
R70
51.1_1%
C495
0.1UF
R368
62_1%
R401
100_1%
T
T
C337
0.1UF
R72
62_1%
R264 51_1%
R94 56_1%
C412
0.1UF
L98
4.7uH_SMD_30%
1 2
C415
1UF
T
R111
2.2K
C399
220P
R82 680
R370 51
T
R402
4.7K
R306 150
R425 56_1%
T
C493 0.1UF
1 2
R13 51.1_1%
R400 49.9_1%
R350
51
R103
75
C336
220P
R71 56_1%
R95 56_1%
C376
10U(0805)
R73
62_1%
C405
220P
L99
4.7uH_SMD_30%
1 2
T
R81
27
R305
51_1%
R290 1.5K
T
T
R304
56_1%
R403 10K
U20
EN1617
15
12
14
6
10
1
5
9
13
16
2
3
4
11
7
8
STBY#
SMBDATA
SMBCLK
ADD1
ADD0
NC/CRIT1
NC/CRIT0
NC/OS#
NC
NC
VCC
DXP
DXN
ALERT#
GND
GND
R371 10K
R93
51_1%
JCPU1B
NORTHWOOD478
AC1
V5
A5
AC26
AD26
AE25
L5
R5
P1
E5
D1
F6
F20
AA6
AA21
W23
P23
J23
F21
W22
R22
K22
E22
AF23
AF22
AC3
V6
B6
Y4
AA3
W5
AB2
H5
H2
J6
G1
G4
H6
G2
F3
E3
D2
E2
D4
C1
F7
E6
D5
B3
C4
A2
C3
B2
B5
C6
AB26
AB23
AB25
A4
V21
P26
G25
E21
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
AE23
AD20
AD22
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
J2
J22
J25
J5
K21
R1
R23
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5
G6
R26
E11
E1
F8
G21
G24
T3
T24
T21
G3 R4
AF3
AD6
AD5
L24
AF4
C22
AP0
AP1
VCC_SENSE
ITP_CLK0
ITP_CLK1
DBRESET
ADSTB0
ADSTB1
COMP1
LINT1
LINT0
GTLREF3
GTLREF2
GTLREF1
GTLREF0
STBP3
STBP2
STBP1
STBP0
STBN3
STBN2
STBN1
STBN0
BCLK1
BCLK0
IERR
MCERR
FERR
STPCLK
BINIT
INIT
RSP
DBSY
DRDY
TRDY
ADS
LOCK
BR0
BNR
HIT
HITM
BPRI
DEFER
TCK
TDI
TMS
TRST
TDO
THERMDA
THERMDC
THERMTRIP
PROCHOT
IGNNE
SMI
A20M
SLP
PWRGOOD
RESET
VSS_SENSE
DB#3
DB#2
DB#1
DB#0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCCIOPLL
VCCA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VCCVIDPRG
BSEL0
BSEL1
COMP0
VCCVID
VSS
ITP/TAP TERMINATION
CLOSE TO ITP PORT
CPU SIGNAL TERMINALION
CLOSE TO CPU
20
mils
ITP/TAP TERMINATION
CLOSE TO CPU
NEAR U18
Sheet 3 of 42
Socket 478 & ITP
2 of 2