Compaq 21264 Network Card User Manual


 
5–38 Internal Processor Registers
21264/EV68A Hardware Reference Manual
Cbox CSRs and IPRs
5.4.4 Cbox WRITE_MANY Chain Description
The WRITE_MANY chain order is contained in Table 5–25. Note the following:
Many CSRs are duplicated for ease of hardware implementation. These CSR names
are indicated in italics and have two leading asterisks.
Only a brief description of each CSR is given. The functional description of these
CSRs is contained in Chapter 3.
CFR_GCLK_DELAY[0:3] Number of GCLK cycles to delay internal ClkFwdRst.
CFR_EV6CLK_DELAY[0:2] Number of EV6Clk_x cycles to delay internal ClkFwdRst.
CFR_FRMCLK_DELAY[0:1] Number of FrameClk_x cycles to delay internal ClkFwdRst.
BC_LATE_WRITE_NUM[0:2] Duplicate CSR.
BC_CPU_LATE_WRITE_NUM[1:0] Duplicate CSR.
JITTER_CMD[0] Add one GCLK cycle to the SYSDC write path.
FAST_MODE_DISABLE[0] Duplicate CSR.
SYSDC_DELAY[3:0] Number of GCLK cycles to delay SysDc fill commands before
action by the Cbox.
DATA_VALID_DLY[1:0] Number of Bcache clock cycles to delay signal SysDataInValid
before sample by the Cbox.
BC_DDM_FALL_EN Duplicate CSR.
BC_DDM_RISE_EN Duplicate CSR.
BC_CPU_CLK_DELAY[0:1] Delay of Bcache clock for 0, 1, 2, 3 GCLK cycles.
BC_FDBK_EN[0:7] CSR to program the Bcache forwarded clock shift register feedback
points.
BC_CLK_LD_VECTOR[0:15] CSR to program the Bcache forwarded clock shift register load val-
ues.
BC_BPHASE_LD_VECTOR[0:3] CSR to program the Bcache forwarded clock b-phase enables.
SYS_DDM_FALL_EN Duplicate CSR.
SYS_DDM_RISE_EN Duplicate CSR.
SYS_CPU_CLK_DELAY[0:1] Delay of 0..3 GCLK cycles between the forwarded clock out and
address/data.
SYS_FDBK_EN[0:7] CSR to program the system forwarded clock shift register feedback
points.
SYS_CLK_LD_VECTOR[0:15] CSR to program the system forwarded clock shift register load val-
ues.
SYS_BPHASE_LD_VECTOR[0:3] CSR to program the system forwarded clock b-phase enables.
SYS_FRAME_LD_VECTOR[0:4] CSR to program the ratio between frame clock and system for-
warded clock.
SYSDC_DELAY[4] Fifth SYSDC_DELAY bit.
Table 5–24 Cbox WRITE_ONCE Chain Order (Continued)
Cbox WRITE_ONCE Chain Description