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21264/EV68A Hardware Reference Manual
Cache and External Interfaces 4–1
4
Cache and External Interfaces
This chapter describes the 21264/EV68A cache and external interface, which includes
the second-level cache (Bcache) interface and the system interface. It also describes
locks, interrupt signals, and ECC/parity generation. It is organized as follows:
• Introduction to the external interfaces
• Physical address considerations
• Bcache structure
• Victim data buffer
• Cache coherency
• Lock mechanism
• System port
• Bcache port
• Interrupts
Chapter 3 lists and defines all 21264/EV68A hardware interface signal pins. Chapter 9
describes the 21264/EV68A hardware interface electrical requirements.
4.1 Introduction to the External Interfaces
A 21264/EV68A-based system can be divided into three major sections:
• 21264/EV68A microprocessor
• Second-level Bcache
• System interface logic
– Optional duplicate tag store
– Optional lock register
– Optional victim buffers
The 21264/EV68A external interface is flexible and mandates few design rules, allow-
ing a wide range of prospective systems. The external interface is composed of the
Bcache interface and the system interface.
• Input clocks must have the same frequency as their corresponding output clock. For
example, the frequency of SysAddInClk_L must be the same as
SysAddOutClk_L.