Filter
Top Products
4–4 Cache and External Interfaces
21264/EV68A Hardware Reference Manual
Physical Address Considerations
4.1.1.1 Commands and Addresses
The system sends probe and data movement commands to the 21264/EV68A. The
21264/EV68A can hold up to eight probe commands from the system. The system con-
trols the number of outstanding probe commands and must ensure that the 21264/
EV68A 8-entry probe queue does not overflow.
The Cbox contains an 8-entry miss buffer (MAF) and an 8-entry victim buffer (VAF).
A miss occurs when the 21264/EV68A probes the Bcache but does not find the
addressed block. The 21264/EV68A can queue eight cache misses to the system in its
MAF.
4.1.2 Second-Level Cache (Bcache) Interface
The 21264/EV68A Cbox provides control signals and an interface for a second-level
cache, the Bcache. The 21264/EV68A supports a Bcache from 1MB to 16MB, with 64-
byte blocks. A 128-bit data bus is used for transfers between the 21264/EV68A and the
Bcache. The Bcache must be comprised of synchronous static RAMs (SSRAMs) and
must contain either one, two, or three internal registers. All Bcache control and address
pins are clocked synchronously on Bcache cycle boundaries. The Bcache clock rate
varies as a multiple of the CPU clock cycle in half-cycle increments from 1.5 to 4.0,
and in full-cycle increments of 5, 6, 7, and 8 times the CPU clock cycle. The 1.5 multi-
ple is only available in dual-data mode.
4.2 Physical Address Considerations
The 21264/EV68A supports a 44-bit physical address space that is divided equally
between memory space and I/O space. Memory space resides in the lower half of the
physical address space (PA[43] = 0) and I/O space resides in the upper half of the phys-
ical address space (PA[43] = 1). The 21264/EV68A recognizes these spaces internally.
The 21264/EV68A-generated external references to memory space are always of a
fixed 64-byte size, though the internal access granularity is byte, word, longword, or
quadword. All 21264/EV68A-generated external references to memory or I/O space
are physical addresses that are either successfully translated from a virtual address or
produced by PALcode. Speculative execution may cause a reference to nonexistent
memory. Systems must check the range of all addresses and report nonexistent
addresses to the 21264/EV68A.
Table 4–1 describes the translation of internal references to external interface refer-
ences. The first column lists the instructions used by the programmer, including load
(LDx) and store (STx) instructions of several sizes. The column headings are described
here:
• DcHit (block was found in the Dcache)
• DcW (block was found in a writable state in the Dcache)
• BcHit (block was found in the Bcache)
• BcW (block was found in a writable state in the Bcache)
• Status and Action (status at end of instruction and action performed by the 21264/
EV68A)