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4–58 Alpha Architecture Handbook
Description:
MSKxL and MSKxH set selected bytes of register Ra to zero, storing the result in register Rc.
Register Rbv’<2:0> selects the starting position of the field of zero bytes, and the function
code selects the maximum width: 1, 2, 4, or 8 bytes. The instructions generate a byte, word,
longword, or quadword field of zeros that can spread across two registers at an arbitrary byte
alignment.
Notes:
The comments in the examples below assume that the effective address (ea) of X(R11) is such
that (ea mod 8) = 5, the value of the aligned quadword containing X(R11) is CBAx xxxx, the
value of the aligned quadword containing X+7(R11) is yyyH GFED, the value to be stored
from R5 is HGFE DCBA, and the datum is little-endian. Slight modifications similar to those
in Section 4.6.2 apply to big-endian data.
The examples below are the most general case; if more information is known about the value
or intended alignment of X, shorter sequences can be used.
The intended sequence for storing an unaligned quadword R5 at address X(R11) is:
LDA R6, X(R11) ; R6<2:0> = (X mod 8) = 5
LDQ_U R2, X+7(R11) ; Ignores va<2:0>, R2 = yyyH GFED
LDQ_U R1, X(R11) ; Ignores va<2:0>, R1 = CBAx xxxx
INSQH R5, R6, R4 ; R4 = 000H GFED
INSQL R5, R6, R3 ; R3 = CBA0 0000
MSKQH R2, R6, R2 ; R2 = yyy0 0000
MSKQL R1, R6, R1 ; R1 = 000x xxxx
OR R2, R4, R2 ; R2 = yyyH GFED
OR R1, R3, R1 ; R1 = CBAx xxxx
STQ_U R2, X+7(R11) ; Must store high then low for
STQ_U R1, X(R11) ; degenerate case of aligned QW
The intended sequence for storing an unaligned longword R5 at X is:
LDA R6, X(R11) ; R6<2:0> = (X mod 8) = 5
LDQ_U R2, X+3(R11) ; Ignores va<2:0>, R2 = yyyy yyyD
LDQ_U R1, X(R11) ; Ignores va<2:0>, R1 = CBAx xxxx
INSLH R5, R6, R4 ; R4 = 0000 000D
INSLL R5, R6, R3 ; R3 = CBA0 0000
MSKLH R2, R6, R2 ; R2 = yyyy yyy0
MSKLL R1, R6, R1 ; R1 = 000x xxxx
OR R2, R4, R2 ; R2 = yyyy yyyD
OR R1, R3, R1 ; R1 = CBAx xxxx
STQ_U R2, X+3(R11) ; Must store high then low for
STQ_U R1, X(R11) ; degenerate case of aligned