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Instruction Descriptions 4–63
All floating-point loads and stores may take memory management faults (access control viola-
tion, translation not valid, fault on read/write, data alignment).
The floating-point enable (FEN) internal processor register (IPR) allows system software to
restrict access to the floating-point registers.
If a floating-point instruction is implemented and FEN = 0, attempts to execute the instruction
cause a floating disabled fault.
If a floating-point instruction is not implemented, attempts to execute the instruction cause an
Illegal Instruction Trap. This rule holds regardless of the value of FEN.
An Alpha implementation may provide both VAX and IEEE floating-point operations, either,
or none.
Some floating-point instructions are common to the VAX and IEEE subsets, some are VAX
only, and some are IEEE only. These are designated in the descriptions that follow. If either
subset is implemented, all the common instructions must be implemented.
An implementation that includes IEEE floating-point may subset the ability to perform round-
ing to plus infinity and minus infinity. If not implemented, instructions requesting these
rounding modes take Illegal Instruction Trap.
An implementation that includes IEEE floating-point may implement any subset of the Trap
Disable flags (DNOD, DZED, INED, INVD, OVFD, and UNFD) and Denormal Control flags
(DNZ and UNDZ) in the FPCR:
• If a Trap Disable flag is not implemented, then the corresponding trap occurs as usual.
• If DNZ is not implemented, then any IEEE operation with a denormal input must take
an Invalid Operation Trap.
• If UNDZ is not implemented, then any IEEE operation that includes a /S qualifier that
underflows must take an Underflow Trap.
• If DZED is implemented, then IEEE division of 0/0 must be treated as an invalid opera-
tion instead of a division by zero.
Any unimplemented bits in the FPCR are read as zero and ignored when set.
4.7.3 Definitions
The following definitions apply to Alpha floating-point support.
Alpha finite number
A floating-point number with a definite, in-range value. Specifically, all numbers in the inclu-
sive ranges –MAX through –MIN, zero, and +MIN through +MAX, where MAX is the largest
non-infinite representable floating-point number and MIN is the smallest non-zero represent-
able normalized floating-point number.