Compaq ECQD2KCTE Laptop User Manual


 
4–68 Alpha Architecture Handbook
4.7.6.2 High-Performance VAX-Format Arithmetic
This model provides arithmetic operations on VAX finite numbers. An imprecise arithmetic
trap is generated by any operation that involves non-finite numbers, floating overflow, and
divide-by-zero exceptions.
This model is implemented by using VAX floating-point instructions with a trap qualifier other
than /S, /SU, or /SV. Each instruction can determine whether it also traps on underflow or inte-
ger overflow. This model does not require the overhead of an operating system completion
handler and can be the faster of the two VAX models.
4.7.6.3 IEEE-Compliant Arithmetic
This model provides floating-point arithmetic that fully complies with the IEEE Standard for
Binary Floating-Point Arithmetic. It provides all of the exception status flags that are in the
standard. It provides a default where all traps and faults are disabled and where IEEE
non-finite values are used in lieu of exceptions.
Alpha operating systems provide additional mechanisms that allow the user to specify dynami-
cally which exception conditions should trap and which should proceed without trapping. The
operating systems also include mechanisms that allow alternative handling of denormal val-
ues. See Appendix B and the appropriate operating system documentation for a description of
these mechanisms.
This model is implemented by using IEEE floating-point instructions with the /SUI
or /SVI trap qualifiers. The performance of this model depends on how often computations
involve inexact results and non-finite operands and results. Performance also depends on how
the Alpha system chooses to trade off implementation complexity between hardware and oper-
ating system completion handlers (see Section 4.7.7.3). This model provides acceptable
performance on Alpha systems that implement the inexact disable (INED) bit in the FPCR.
Performance may be slow if the INED bit is not implemented.
4.7.6.4 IEEE-Compliant Arithmetic Without Inexact Exception
This model is similar to the model in Section 4.7.6.3, except this model does not signal inexact
results either by the inexact status flag or by trapping. Combining routines that are compiled
with this model and routines that are compiled with the model in Section 4.7.6.3 can give an
application better control over testing when an inexact operation will affect computational
accuracy.
This model is implemented by using IEEE floating-point instructions with the /SU or /SV trap
qualifiers. The performance of this model depends on how often computations involve
non-finite operands and results. Performance also depends on how an Alpha system chooses to
trade off implementation complexity between hardware and operating system completion han-
dlers (see Section 4.7.7.3).