Compaq ECQD2KCTE Laptop User Manual


 
Instruction Descriptions 4–69
4.7.6.5 High-Performance IEEE-Format Arithmetic
This model provides arithmetic operations on IEEE finite numbers and notifies applications of
all exceptional floating-point operations. An imprecise arithmetic trap is generated by any
operation that involves non-finite numbers, floating overflow, divide-by-zero, and invalid
operations. Underflow results are set to zero. Conversion to integer results that overflow are set
to the low-order bits of the integer value.
This model is implemented by using IEEE floating-point instructions with a trap qualifier other
than /SU, /SV, /SUI, or /SVI. Each instruction can determine whether it also traps on under-
flow or integer overflow. This model does not require the overhead of an operating system
completion handler and can be the fastest of the three IEEE models.
4.7.7 Trapping Modes
There are six exceptions that can be generated by floating-point operate instructions, all sig-
naled by an arithmetic exception trap. These exceptions are:
Invalid operation
Division by zero
Overflow
Underflow
Inexact result
Integer overflow (conversion to integer only)
4.7.7.1 VAX Trapping Modes
This section describes the characteristics of the four VAX trapping modes, which are summa-
rized in Table 4–8.
When no trap mode is specified (the default):
Arithmetic is performed on VAX finite numbers.
Operations give imprecise traps whenever the following occur:
an operand is a non-finite number
a floating overflow
a divide-by-zero
Traps are imprecise and it is not always possible to determine which instruction trig-
gered a trap or the operands of that instruction.
An underflow produces a zero result without trapping.
A conversion to integer that overflows uses the low-order bits of the integer as the
result without trapping.
The result of any operation that traps is UNPREDICTABLE.