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Introduction 1–5
Branch Instructions
Conditional branch instructions can test a register for positive/negative or for zero/nonzero,
and they can test integer registers for even/odd. Unconditional branch instructions can write a
return address into a register.
There is also a calculated jump instruction that branches to an arbitrary 64-bit address in a
register.
Load/Store Instructions
Load and store instructions move 8-bit, 16-bit, 32-bit, or 64-bit aligned quantities from and to
memory. Memory addresses are flat 64-bit virtual addresses with no segmentation.
The VAX floating-point load/store instructions swap words to give a consistent register format
for floating-point operations.
A 32-bit integer datum is placed in a register in a canonical form that makes 33 copies of the
high bit of the datum. A 32-bit floating-point datum is placed in a register in a canonical form
that extends the exponent by 3 bits and extends the fraction with 29 low-order zeros. The 32-
bit operates preserve these canonical forms.
Compilers, as directed by user declarations, can generate any mixture of 32-bit and 64-bit oper-
ations. The Alpha architecture has no 32/64 mode bit.
Integer Operate Instructions
The integer operate instructions manipulate full 64-bit values and include the usual assortment
of arithmetic, compare, logical, and shift instructions.
There are just three 32-bit integer operates: add, subtract, and multiply. They differ from their
64-bit counterparts only in overflow detection and in producing 32-bit canonical results.
There is no integer divide instruction.
The Alpha architecture also supports the following additional operations:
• Scaled add/subtract instructions for quick subscript calculation
• 128-bit multiply for division by a constant, and multiprecision arithmetic
• Conditional move instructions for avoiding branch instructions
• An extensive set of in-register byte and word manipulation instructions
• A set of multimedia instructions that support graphics and video
Integer overflow trap enable is encoded in the function field of each instruction, rather than
kept in a global state bit. Thus, for example, both ADDQ/V and ADDQ opcodes exist for spec-
ifying 64-bit ADD with and without overflow checking. That makes it easier to pipeline
implementations.