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5–6 Alpha Architecture Handbook
5.5 Data Sharing
In a multiprocessor environment, writes to shared data must be synchronized by the
programmer.
5.5.1 Atomic Change of a Single Datum
The ordinary STL and STQ instructions can be used to perform an atomic change of a shared
aligned longword or quadword. ("Change" means that the new value is not a function of the old
value.) In particular, an ordinary STL or STQ instruction can be used to change a variable that
could be simultaneously accessed via an LDx_L/STx_C sequence.
5.5.2 Atomic Update of a Single Datum
The load-locked/store-conditional instructions may be used to perform an atomic update of a
shared aligned longword or quadword. ("Update" means that the new value is a function of the
old value.)
The following sequence performs a read-modify-write operation on location x. Only regis-
ter-to-register operate instructions and branch fall-throughs may occur in the sequence:
try_again:
LDQ_L R1,x
<modify R1>
STQ_C R1,x
BEQ R1,no_store
:
no_store:
<code to check for excessive iterations>
BR try_again
If this sequence runs with no exceptions or interrupts, and no other processor writes to loca-
tion x (more precisely, the locked range including x) between the LDQ_L and STQ_C
instructions, then the STQ_C shown in the example stores the modified value in x and sets R1
to 1. If, however, the sequence encounters exceptions or interrupts that eventually continue the
sequence, or another processor writes to x, then the STQ_C does not store and sets R1 to 0. In
this case, the sequence is repeated by the branches to no_store and try_again. This repetition
continues until the reasons for exceptions or interrupts are removed and no interfering store is
encountered.
To be useful, the sequence must be constructed so that it can be replayed an arbitrary number
of times, giving the same result values each time. A sufficient (but not necessary) condition is
that, within the sequence, the set of operand destinations and the set of operand sources are
disjoint.
Note:
A sufficiently long instruction sequence between LDx_L and STx_C will never complete,
because periodic timer interrupts will always occur before the sequence completes. The
rules in Section A.5 describe sequences that will eventually complete in all Alpha
implementations.