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5–10 Alpha Architecture Handbook
an ADDL2 to update a variable that is shared between a "MAIN" routine and an AST
routine, if running on a single processor. In the Alpha architecture, a programmer must
deal with AST shared data by using multiprocessor shared data sequences.
5.6 Read/Write Ordering
This section applies to programs that run on multiple processors or on one or more processors
that are interacting with DMA I/O devices. To a program running on a single processor and not
interacting with DMA I/O devices, all memory accesses appear to happen in the order speci-
fied by the programmer. This section deals with predictable read/write ordering across multiple
processors and/or DMA I/O devices.
The order of reads and writes done in an Alpha implementation may differ from that specified
by the programmer.
For any two memory accesses A and B, either A must occur before B in all Alpha implementa-
tions, B must occur before A, or they are UNORDERED. In the last case, software cannot
depend upon one occurring first: the order may vary from implementation to implementation,
and even from run to run or moment to moment on a single implementation.
If two accesses cannot be shown to be ordered by the rules given, they are UNORDERED and
implementations are free to do them in any order that is convenient. Implementations may take
advantage of this freedom to deliver substantially higher performance.
The discussion that follows first defines the architectural issue sequence of memory accesses
on a single processor, then defines the (partial) ordering on this issue sequence that all Alpha
implementations are required to maintain.
The individual issue sequences on multiple processors are merged into access sequences at
each shared memory location. The discussion defines the (partial) ordering on the individual
access sequences that all Alpha implementations are required to maintain.
The net result is that for any code that executes on multiple processors, one can determine
which memory accesses are required to occur before others on all Alpha implementations and
hence can write useful shared-variable software.
Software writers can force one access to occur before another by inserting a memory barrier
instruction (MB, WMB, or CALL_PAL IMB) between the accesses.
5.6.1 Alpha Shared Memory Model
An Alpha system consists of a collection of processors, I/O devices (and possibly a bridge to
connect remote I/O devices), and shared memories that are accessible by all processors.
Note:
An example of an unshared location is a physical address in I/O space that refers to a CSR
that is local to a processor and not accessible by other processors.
A processor is an Alpha CPU.