Compaq ECQD2KCTE Laptop User Manual


 
System Architecture and Programming Implications 5–11
In most systems, DMA I/O devices or other agents can read or write shared memory locations.
The order of accesses by those agents is not completely specified in this document. It is possi-
ble in some systems for read accesses by I/O devices or other agents to give results indicating
some reordering of accesses. However, there are guarantees that apply in all systems. See Sec-
tion 5.6.4.7.
A shared memory is the primary storage place for one or more locations.
A location is a byte, specified by its physical address. Multiple virtual addresses may map to
the same physical address. Ordering considerations are based only on the physical address.
This definition of location specifically includes locations and registers in memory mapped I/O
devices and bridges to remote I/O (for example, Mailbox Pointer Registers, or MBPRs).
Implementation Note:
An implementation may allow a location to have multiple physical addresses, but the rules
for accesses via mixtures of the addresses are implementation-specific and outside the
scope of this section. Accesses via exactly one of the physical addresses follow the rules
described next.
Each processor may generate accesses to shared memory locations. There are six types of
accesses:
1. Instruction fetch by processor i to location x, returning value a, denoted Pi:I<4>(x,a).
2. Data read (including load-locked) by processor i to location x, returning value a,
denoted Pi:R<size>(x,a).
3. Data write (including successful store-conditional) by processor i to location x, storing
value a, denoted Pi:W<size>(x,a).
4. Memory barrier issued by processor i, denoted Pi:MB.
5. Write memory barrier issued by processor i, denoted Pi:WMB.
6. I-stream memory barrier issued by processor i, denoted Pi:IMB.
The first access type is also called an I-stream access or I-fetch. The next two are also called
D-stream accesses. The first three types are collectively called read/write accesses, denoted
Pi:Op<m>(x,a), where m is the size of the access in bytes, x is the (physical) address of the
access, and a is a value representable in m bytes; for any k in the range 0..m–1, byte k of value
a (where byte 0 is the low-order byte) is the value written to or read from location x+k by the
access. This relationship reflects little-endian addressing; big-endian addressing representation
is as described in Chapter 2.
The last three types collectively are called barriers or memory barriers.
The size of a read/write access is 8 for a quadword access, 4 for a longword access (including
all instruction fetches), 2 for a word access, or 1 for a byte access. All read/write accesses in
this chapter are naturally aligned. That is, they have the form Pi:Op<m>(x,a), where the
address x is divisible by size m.
The word "access" is also used as a verb; a read/write access Pi:Op<m>(x,a) accesses byte z if
x z < x+m. Two read/write accesses Op1<m>(x,a) and Op2<n>(y,b) are defined to overlap if