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System Architecture and Programming Implications 5–13
Where "overlap" denotes the condition max(x,y) < min(x+m,y+n).
For two accesses u and v issued by processor Pi, if u precedes v by processor issue constraint,
then u precedes v in BEFORE order. u and v on Pi are ordered by processor issue constraint if
any of the following applies:
1. The entry in Table 5–1 indicated by the access type of u (1st) and v (2nd) indicates the
accesses are ordered.
2. u and v are both writes to memory-like regions and there is a WMB between u and v in
processor issue sequence.
3. u and v are both writes to non-memory-like regions and there is a WMB between u and
v in processor issue sequence.
4. u is a TB fill that updates a PTE, for example, a PTE read in order to satisfy a TB miss,
and v is an I- or D-stream access using that PTE (see Sections 5.6.4.3 and 5.6.4.4).
In Table 5–1, 1st and 2nd refer to the ordering of accesses in the processor issue sequence.
Note that Table 5–1 imposes no direct constraint on the ordering relationship between non-
overlapping read/write accesses, though there may be indirect constraints due to the transitivity
of BEFORE (⇐ ). Conditions 2 through 4, above, impose ordering constraints on some pairs of
nonoverlapping read/write accesses.
Table 5–1 permits a read access Pi:R<n>(y,b) to be ordered BEFORE an overlapping write
access Pi:W<m>(x,a) that precedes the read access in processor issue order. This asymmetry
for reads allows reads to be satisfied by using data from an earlier write in processor issue
sequence by the same processor (for example, by hitting in a write buffer) before the write
completes. The write access remains "visible" to the read access; "visibility" is described in
Sections 5.6.1.5 and 5.6.1.6 and illustrated in Litmus Test 11 in Section 5.6.2.11.
An I-fetch Pi:I<4>(y,b) may also be ordered BEFORE an overlapping write Pi:W<m>(x,a) that
precedes it in processor issue sequence. In that case, the write may, but need not, be visible to
the I-fetch. This asymmetry in Table 5–1 allows writes to the I-stream to be incoherent until a
CALL_PAL IMB is executed.
Implementations are free to perform memory accesses from a single processor in any sequence
that is consistent with processor issue constraints.
Table 5–1: Processor Issue Constraints
1st↓ 2nd → Pi:I<n=4>(y,b) Pi:R<n>(y,b) Pi:W<n>(y,b) Pi:MB Pi:IMB
Pi:I<m=4>(x,a) ⇐ if overlap ⇐ if overlap ⇐⇐
Pi:R<m>(x,a) ⇐ if overlap ⇐ if overlap ⇐⇐
Pi:W<m>(x,a) ⇐ if overlap ⇐⇐
Pi:MB ⇐⇐⇐⇐
Pi:IMB ⇐⇐⇐⇐⇐