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5–28 Alpha Architecture Handbook
will detect the writes of the shared data before detecting the flag write, interrupt, or device reg-
ister write.
This implies that after a processor has prepared a data buffer to be read from memory by a
DMA I/O device (such as writing a buffer to disk), the processor must execute an MB before
starting the I/O. The I/O device, after receiving the start signal, must logically execute an MB
before reading the data buffer, and the buffer must be located in a memory-like physical mem-
ory region.
There are methods of communicating data that may work in some systems but are not guaran-
teed in all systems. Two notable examples are:
1. If an Alpha processor writes a location implemented in a component located on an I/O
bus in the system, then executes a memory barrier, then writes a flag in some memory
location (in a memory-like or non-memory-like region), a device on the I/O bus may be
able to detect (via read access) the result of the flag in memory write and the write of
the location on the I/O bus out of order (that is, in a different order than the order in
which the Alpha processor wrote those locations).
2. If an Alpha processor writes a location that is a control register within an I/O device,
then executes a memory barrier, then writes a location in memory (in a memory-like or
non-memory-like region), the I/O device may be able to detect (via read access) the
result of the memory write before receiving and responding to the write of its own con-
trol register.
In almost every case, a mechanism that ensures the completion of writes to control register
locations within I/O devices is provided. The normal and strongly recommended mechanism is
to read a location after writing it, which guarantees that the write is complete. In any case, all
systems that use a particular I/O device should provide the same mechanism for that device.
5.6.4.8 Multiple Processors Writing to a Single I/O Device
Generally, for multiple processors to cooperate in writing to a single I/O device, the first pro-
cessor must write to the device, execute an MB, then notify other processors. Another
processor that intends to write the same I/O device after the first processor must receive the
notification, execute an MB, and then write to the I/O device. For example:
First Processor Second Processor
:
Write CSR_A
MB
Write flag (in memory) ⇒ Read flag (in memory)
MB
Write CSR_B
: