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6–8 Alpha Architecture Handbook
6.7.3 Instruction Memory Barrier
Format:
Operation:
{Make instruction stream coherent with data stream}
Exceptions:
Instruction mnemonics:
Description:
An IMB instruction must be executed after software or I/O devices write into the instruction
stream or modify the instruction stream virtual address mapping, and before the new value is
fetched as an instruction. An implementation may contain an instruction cache that does not
track either processor or I/O writes into the instruction stream. The instruction cache and mem-
ory are made coherent by an IMB instruction.
If the instruction stream is modified and an IMB is not executed before fetching an instruction
from the modified location, it is UNPREDICTABLE whether the old or new value is fetched.
Software Note:
In a multiprocessor environment, executing an IMB on one processor does not affect
instruction caches on other processors. Thus, a single IMB on one processor is
insufficient to guarantee that all processors see a modification of the instruction stream.
The cache coherency and sharing rules are described in Console Interface (III), Chapter 2, in
the Alpha Architecture Reference Manual.
CALL_PAL IMB
!PALcode format
None
CALL_PAL IMB I-stream Memory Barrier