Compaq ECQD2KCTE Laptop User Manual


 
11–5
retsys Return from system service call exception
The retsys instruction returns from a system service call exception by unwind-
ing the trap frame and returning to the code stream that was executing when the
original exception was initiated. In addition, retsys accepts a parameter to set
software interrupt requests that became pending while the exception was han-
dled.
rfe Return from trap or interrupt
The rfe instruction returns from exceptions by unwinding the trap frame and
returning to the code stream that was executing when the original exception
was initiated. In addition, rfe accepts a parameter to set software interrupt
requests that became pending while the exception was handled.
ssir Set software interrupt request
The ssir instruction sets software interrupt requests by setting the appropriate
bits in the SIRR internal processor register.
swpctx Swap thread context
The swpctx instruction swaps the privileged portions of thread context. Thread
context is swapped by establishing the new IKSP, THREAD, and TEB internal
processor register values.
swpirql Swap the current interrupt request level
The swpirql instruction swaps the current IRQL field in the PSR internal pro-
cessor register by setting the processor so that only permitted interrupts are
enabled for the new IRQL. Swpirql updates the IRQL field and returns the pre-
vious IRQL.
swpksp Swap the initial kernel stack pointer for the current thread
The swpksp instruction returns the value of the previous IKSP internal proces-
sor register and writes a new IKSP for the currently executing thread.
swppal Swap the currently executing PALcode
The swppal instruction swaps the currently executing PALcode by transferring
to the base address of the new PALcode image in the PALcode environment.
swpprocess Swap process context (swap address space)
The swpprocess instruction swaps the privileged process context by changing
the address space for the currently executing thread.
Table 11–2 : Privileged Windows NT Alpha PALcode Instruction Summary (Continued)
Mnemonic Operation and description