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tbia Translation buffer invalidate all
The tbia instruction invalidates all translations and virtual cache blocks within
the processor.
tbim Translation buffer invalidate multiple
The tbim instruction invalidates multiple virtual translations for the current
ASN. The translation for the virtual address must be invalidated in all processor
translation buffers and virtual caches.
tbimasn Translation buffer invalidate multiple for ASN
The tbimasn instruction invalidates multiple virtual translations for a specified
ASN. The translation for the virtual addresses must be invalidated in all proces-
sor translation buffers and virtual caches.
tbis Translation buffer invalidate single
The tbis instruction invalidates a single virtual translation. The translation for
the passed virtual address must be invalidated in all processor translation buff-
ers and virtual caches.
tbisasn Translation buffer invalidate single for ASN
The tbisasn instruction invalidates a single virtual translation for a specified
address space. The translation for the passed virtual address must be invali-
dated in all processor translation buffers and virtual caches.
wrentry Write kernel exception entry routine
The wrentry instruction provides the registry of exception handling routines for
the exception classes. The kernel must use wrentry to register an exception han-
dler for each of the exception classes.
wrmces Write the machine check error summary register
The wrmces instruction writes new values for the MCES internal processor
register and returns the previous values of that register.
wrperfmon Write performance counter interrupt control information
The wrperfmon instruction writes control information for the two processor
performance counters. One parameter identifies the selected performance
counter, while another controls whether the selected performance counter is
enabled or disabled. The instruction returns the previous enable state for the
selected performance counter.
Table 11–2 : Privileged Windows NT Alpha PALcode Instruction Summary (Continued)
Mnemonic Operation and description