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Software Considerations A–9
A.4 Code Sequences
The following section describes code sequences.
A.4.1 Aligned Byte/Word (Within Register) Memory Accesses
The instruction sequences given in Section 4.6 for byte-within-register accesses are worst-case
code. More importantly, they do not reflect the instructions available with the BWX extension,
described in the Sections 4.2.2, 4.2.6, and 4.6.5, and in Section D.3. If the BWX extension
instructions are available, it is wise to consider them rather than the sequences that follow.
The following sequences are appropriate if the BWX extension instructions are not available.
In the common case of accessing a byte or aligned word field at a known offset from a pointer
that is expected to be at least longword aligned, the common-case code is much shorter.
"Expected" means that the code should run fast for a longword-aligned pointer and trap for
unaligned. The trap handler may at its option fix up the unaligned reference.
For access at a known offset D from a longword-aligned pointer Rx, let D.lw be D rounded
down to a multiple of 4 ((D div 4)*4), and let D.mod be D mod 4.
In the common case, the intended sequence for loading and zero-extending an aligned word is:
LDL R1,D.lw(Rx) ! Traps if unaligned
EXTWL R1,#D.mod,R1 ! Picks up word at byte 0 or byte 2
In the common case, the intended sequence for loading and sign-extending an aligned word is:
LDL R1,D.lw(Rx) ! Traps if unaligned
SLL R1,#48-8*D.mod,R1 ! Aligns word at high end of R1
SRA R1,#48,R1 ! SEXT to low end of R1
Prefetch with
Modify Intent
LDS F31, xxx (Rn) If the load operation hits a dirty, modified,
Dcache block, the instruction is dismissed. Oth-
erwise, the addressed cache block is allocated
into the Dcache for write access — its dirty and
modified bits are set.
Prefetch, Evict
Next
LDQ R31, xxx (Rn) Prefetch a cache block and mark that block in an
associated cache to be evicted on the next cache
fill to an associated address. (This operation is
useful to prefetch data that is not to be repeat-
edly referenced.)
Table A–1: Cache Block Prefetching
Type Instructions Operation