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A–16 Alpha Architecture Handbook
A.5 Timing Considerations: Atomic Sequences
A sufficiently long instruction sequence between LDx_L and STx_C will never complete,
because periodic timer interrupts will always occur before the sequence completes. The follow-
ing rules describe sequences that will eventually complete in all Alpha implementations:
• At most 40 operate or conditional-branch (not taken) instructions executed in the
sequence between LDx_L and STx_C.
• At most two I-stream TB-miss faults. Sequential instruction execution guarantees this.
• No other exceptions triggered during the last execution of the sequence.
Implementation Note:
On all expected implementations, this allows for about 50 µsec of execution time, even
with 100 percent cache misses. This should satisfy any requirement for a 1-msec timer
interrupt rate.
SEXTL {Rx/Lit8}, Ry Longword sign-extension of Rx
storing results in Ry
ADDL R31, {Rx/Lit}, Ry
UNOP Universal NOP for both integer
and floating-point code
LDQ_U R31,0(Rx)
Table A–2: Decodable Pseudo-Operations (Stylized Code Forms) (Continued)
Pseudo-Operation
in Listing Meaning
Actual Instruction
Encoding