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B–2 Alpha Architecture Handbook
Overflow and underflow, NaNs, and infinities encountered during software binary to decimal
conversion return strings that specify the conditions.
Alpha hardware supports comparisons of same-format numbers. Software supports compari-
sons of different-format numbers.
In the Alpha architecture, results are true-false in response to a predicate.
Alpha hardware supports the required six predicates and the optional unordered predicate. The
other 19 optional predicates can be constructed from sequences of two comparisons and two
branches.
Alpha hardware supports infinity arithmetic with the compare instructions (CMPTyy). When a
/S qualifier is included, Alpha hardware may optionally support infinity arithmetic when infin-
ity operands are encountered and, together with overflow disable (OVFD) and division by zero
disable (DZED), when infinity is to be generated from finite operands. Otherwise, Alpha hard-
ware supports infinity arithmetic by trapping. That is the case when an infinity operand is
encountered and when an infinity is to be created from finite operands by overflow or division
by zero. An OS completion handler (interposed between the hardware and the IEEE user) pro-
vides correct infinity arithmetic.
When a /S qualifier is included, Alpha hardware may optionally support NaNs and invalid
operations, controlled by the INVD option. Otherwise, Alpha hardware supports NaNs and
invalid operations by trapping when a NaN operand is encountered and when a NaN is to be
created. An OS completion handler (interposed between the hardware and the IEEE user) pro-
vides correct Signaling and Quiet NaN behavior.
In the Alpha architecture, Quiet NaNs do not afford retrospective diagnostic information.
In the Alpha architecture, copying a Signaling NaN without a change of format does not signal
an invalid exception (LDx, CPYSx, and STx do not check for non-finite numbers). Compilers
may generate ADDx F31,Fx,Fy to get the opposite effect.
Alpha hardware fully supports negative zero operands and follows the IEEE rules for creating
negative zero results except for underflow. When a /S qualifier is included, Alpha hardware
may optionally support underflow and denormalized numbers, controlled by the UNFD option.
Otherwise, Alpha hardware supports underflow and denormalized numbers by trapping when a
denormalized operand is encountered, when a denormalized result is created, and when an
underflow occurs. An OS completion handler (interposed between the hardware and the IEEE
user) provides correct denormalized and underflow arithmetic.
Except for the optional trap disable bits in the FPCR, Alpha hardware does not supply IEEE
exception trap behavior; the hardware traps are a superset of the IEEE-required conditions. An
OS completion handler (interposed between the hardware and the IEEE user) provides correct
IEEE exception behavior.
In the Alpha architecture, tininess is detected by hardware after rounding, and loss of accuracy
is detected by software as an inexact result.