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IEEE Floating-Point Conformance B–3
In the Alpha architecture, user signal handlers are supported by compilers and an OS comple-
tion handler (interposed between the hardware and the IEEE user), as described in the next
section.
B.2 Alpha Support for OS Completion Handlers
Alpha floating-point trap behavior is statically controlled by the /S, /U, and /I mode qualifiers
on floating-point instructions. Changing these options usually requires recompiling. Instruc-
tions with any valid qualifier combination that includes the /S qualifier can be dynamically
controlled by the optional trap disable bits and denormal control bits in the FPCR.
Each Alpha implementation may choose how to distribute support for the completion modes
(/S, /SU, /SV, /SUI, and /SVI), between hardware and software. An implementation may
minimize hardware complexity by trapping to implementation software for support of excep-
tions and non-finites. An implementation may choose increased floating-point performance at
the cost of increased hardware complexity by providing hardware support for exceptions and
non-finites.
However completion mode support is distributed, application software on any system that
meets the Alpha architecture specification will see consistent floating-point semantics because
Alpha implementation software provides support for any floating-point feature that is not
directly supported by the hardware.
Each Alpha operating system must include an OS completion handler that does software com-
pletion of instructions that have any valid qualifier combination that includes the /S qualifier,
and that finishes the computation of any floating-point operation that is not completed by the
hardware. The OS completion handler is responsible for providing the result specified by the
architecture. The handler either continues execution of the application program or signals an
exception to the application.
If the exception summary parameter of an arithmetic trap indicates that an instruction requir-
ing software completion caused the trap, the operating system must finish the operation. An
OS completion handler uses the register write mask parameter to ignore instructions in the trap
shadow and to locate the trigger instruction of the arithmetic trap. The handler then uses the
trigger instruction input register values to compute the result in the output register and to
record any appropriate signal status. The handler then continues execution with the instruction
following the trigger instruction, unless the application has requested execution of an optional
signal handler.
It is recommended that the OS completion handler report an enabled IEEE exception to the
user application as a fault, rather than as a trap. When reported as a fault, the reported PC
points to the trigger instruction, rather than after the trigger instruction. Regardless of whether
an enabled fault occurs, it is recommended that the completion trap handler set the result regis-
ter and status flags to the IEEE standard nontrapping results, as defined in the IEEE Standard
section in Section 4.7.10. That behavior makes it possible for the user application to continue
from a fault by stepping over the trigger instruction.
The Floating-Point Control Register (FPCR) contains several trap disable bits and denormal
control bits. Implementation of these bits in the FPCR is optional. A system that includes