Compaq ECQD2KCTE Laptop User Manual


 
2–4 Alpha Architecture Handbook
The F_floating store instruction reorders register bits on the way to memory and does no
checking of the low-order fraction bits. Register bits <61:59> and <28:0> are ignored by the
store instruction.
An F_floating datum is specified by its address A, the address of the byte containing bit 0. The
memory form of an F_floating datum is sign magnitude with bit 15 the sign bit, bits <14:7> an
excess-128 binary exponent, and bits <6:0> and <31:16> a normalized 24-bit fraction with the
redundant most significant fraction bit not represented. Within the fraction, bits of increasing
significance are from 16 through 31 and 0 through 6. The 8-bit exponent field encodes the val-
ues 0 through 255. An exponent value of 0, together with a sign bit of 0, is taken to indicate
that the F_floating datum has a value of 0.
If the result of a VAX floating-point format instruction has a value of zero, the instruction
always produces a datum with a sign bit of 0, an exponent of 0, and all fraction bits of 0. Expo-
nent values of 1..255 indicate true binary exponents of –127..127. An exponent value of 0,
together with a sign bit of 1, is taken as a reserved operand. Floating-point instructions pro-
cessing a reserved operand take an arithmetic exception. The value of an F_floating datum is in
the approximate range 0.29*10**–38 through 1.7*10**38. The precision of an F_floating
datum is approximately one part in 2**23, typically 7 decimal digits. See Section 4.7.
Note:
Alpha implementations will impose a significant performance penalty when accessing
F_floating operands that are not naturally aligned. (A naturally aligned F_floating datum
has zero as the low-order two bits of its address.)
2.2.5.2 G_floating
A G_floating datum in memory is 8 contiguous bytes starting on an arbitrary byte boundary.
The bits are labeled from right to left, 0 through 63, as shown in Figure 2–7.
Figure 2–7: G_floating Datum
Table 2–1: F_floating Load Exponent Mapping (MAP_F)
Memory <14:7> Register <62:52>
1 1111111 1 000 1111111
1 xxxxxxx 1 000 xxxxxxx (xxxxxxx not all 1’s)
0 xxxxxxx 0 111 xxxxxxx (xxxxxxx not all 0’s)
0 0000000 0 000 0000000
S
Exp. Frac.HiFraction Midh :A
:A+4Fraction MidlFraction Lo
43
0
15
16 14
31