Compaq ECQD2KCTE Laptop User Manual


 
E–1
Appendix E
Waivers and Implementation-Dependent
Functionality
This appendix describes waivers to the Alpha architecture and functionality that is specific to
particular hardware implementations.
E.1 Waivers
The following waivers have been passed for the Alpha architecture.
E.1.1 DECchip 21064, DECchip 21066, and DECchip 21068 IEEE Divide
Instruction Violation
The DECchip 21064, DECchip 21066, and DECchip 21068 CPUs violate the architected han-
dling of IEEE divide instructions DIVS and DIVT with respect to reporting Inexact Result
exceptions.
Note:
The DECchip 21064A, DECchip 21066A, and DECchip 21068A CPUs are compliant and
require no waiver. The DECchip 21164 is also compliant.
As specified by the architecture, floating-point exceptions generated by the CPU are recorded
in two places for all IEEE floating-point instructions:
1. If an exception is detected and the corresponding trap is enabled (such as ADD/U for
underflow), the CPU initiates a trap and records the exception in the exception sum-
mary register (EXC_SUM).
2. The exceptions are also recorded as flags that can be tested in the floating-point control
register (FPCR). The FPCR can only be accessed with MTPR/MFPR instructions and
an explicit MT_FPCR is required to clear the FPCR. The FPCR is updated irrespective
of whether the trap is enabled or not.