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Waivers and Implementation-Dependent Functionality E–3
The DECchip 21264 varies from that description, with regard to the WH64 instruction, as
follows:
If any other memory access (ECB, LDx, LDQ_U, STx, STQ_U) is executed on the given
processor between the LDx_L and the STx_C, the sequence above may always fail on
some implementations; hence, no useful program should do this.
If a WH64 memory access is executed on any given 21264 processor between the LDx_L
and STx_C, and:
– The WH64 access is to the same aligned 64-byte block that STx_C is accessing,
and
– No CALL_PAL REI, rei, or rfe instruction has been executed since the most-recent
LDx_L (ensuring that the sequence cannot occur as the result of unfortunate coin-
cidences with interrupts)
then, the load-locked/store-conditional sequence may sometimes fail when it would
otherwise succeed and sometimes succeed when it otherwise would fail; hence no useful
program should do this.
E.2 Implementation-Specific Functionality
The following functionality, although a documentated part of the Alpha architecture, is imple-
mented in a manner that is specific to the particular hardware implementation.
E.2.1 DECchip 21064/21066/21068 Performance Monitoring
Note:
All functions, arguments, and descriptions in this section apply to the DECchip
21064/21064A, 21066/21066A, and 21068/21068A.
PALcode instructions control the DECchip 21064/21066/21068 on-chip performance counters.
For OpenVMS Alpha, the instruction is MTPR_PERFMON; for DIGITAL UNIX and Win-
dows NT Alpha, the instruction is wrperfmon.
The instruction arguments and results are described in the following sections. The scratch reg-
ister usage is operating system specific.
Two on-chip counters count events. The bit width of the counters (8, 12, or 16 bits) can be
selected and the event that they count can be switched among a number of available events.
One possible event is an "external" event. For example, the processor board can supply an
event that causes the counter to increment. In this manner, off-chip events can be counted.
The two counters can be switched independently. There is no hardware support for reading,
writing, or resetting the counters. The only way to monitor the counters is to enable them to
cause an interrupt on overflow.