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E–8 Alpha Architecture Handbook
11:8 PCMUX0 Event selection, counter 0:
3 PC0 Frequency setting, counter 0:
0 PC1 Frequency setting, counter 1:
Table E–2: DECchip 21064/21066/21068 MUX Control Fields in ICCSR Register
(Continued)
Bits Option Description
Value Description
0 Total issues divided by 2
1 Unused
2 Nothing issued, no valid I-stream data
3 Unused
4 All load instructions
5 Unused
6 Nothing issued, resource conflict
7 Unused
8 All branches (conditional, unconditional, JSR, HW_REI)
9 Unused
10 Total cycles
11 Cycles while in PALcode environment
12 Total nonissues divided by 2
13 Unused
14 External event supplied by pin.
15 Unused
Value Description
0 2**16 (65536) events per interrupt
1 2**12 (4096) events per interrupt
Value Description
0 2**12 (4096) events per interrupt
1 2**8 (256) events per interrupt