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Waivers and Implementation-Dependent Functionality E–9
E.2.2 DECchip 21164/21164PC Performance Monitoring
Unless otherwise stated, the term "21164" in this section means implementations of the 21164
at all frequencies.
PALcode instructions control the DECchip 21164/21164PC on-chip performance counters. For
OpenVMS Alpha, the instruction is MTPR_PERFMON; for DIGITAL UNIX and Windows
NT Alpha, the instruction is wrperfmon.
The instruction arguments and results are described in the following sections. The scratch reg-
ister usage is operating system specific.
Three on-chip counters count events. Counters 0 and 1 are 16-bit counters; counter 2 is a 14-bit
counter. Each counter can be individually programmed. Counters can be read and written and
are not required to interrupt. The counters can be collectively restricted according to the pro-
cessor mode.
Processes can be selectively monitored with the PME bit.
E.2.2.1 Performance Monitor Interrupt Mechanism
The performance monitoring interrupt mechanism varies according to the particular operating
system.
For the OpenVMS Alpha Operating System
When a counter overflows and interrupt enabling conditions are correct, the counter causes an
interrupt to PALcode. The PALcode builds an appropriate stack frame. The PALcode then dis-
patches in the form of an exception (not in the form of an interrupt) to the operating system by
vectoring to the SCB performance monitor entry point through SCBB+650
(HWSCB$Q_PERF_MONITOR), at IPL 29, in kernel mode.
An interrupt is generated for each counter overflow. For each interrupt, the status of each
counter overflow is indicated by register R4:
R4 = 0 if performance counter 0 caused the interrupt
R4 = 1 if performance counter 1 caused the interrupt
R4 = 2 if performance counter 2 caused the interrupt
When the interrupt is taken, the PC is saved on the stack frame as the old PC.
For the DIGITAL UNIX Operating System
When a counter overflows and interrupt enabling conditions are correct, the counter causes an
interrupt to PALcode. The PALcode builds an appropriate stack frame and dispatches to the
operating system by vectoring to the interrupt entry point entINT, at IPL 6, in kernel mode.
An interrupt is generated for each counter overflow. For each interrupt, registers a0..a2 are as
follows:
a0 = osfint$c_perf (4)
a1 = scb$v_perfmon (650)
a2 = 0 if performance counter 0 caused the interrupt
a2 = 1 if performance counter 1 caused the interrupt