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Basic Architecture 2–9
A T_floating operand occupies 64 bits in a floating register, arranged as shown in Figure 2–14.
Figure 2–14: T_floating Register Format
The T_floating load instruction performs no bit reordering on input, nor does it perform check-
ing of the input data.
The T_floating store instruction performs no bit reordering on output. This instruction does no
checking of the data; the preceding operation should have specified a T_floating result.
A T_floating datum is specified by its address A, the address of the byte containing bit 0. The
form of a T_floating datum is sign magnitude with bit 63 the sign bit, bits <62:52> an excess-
1023 binary exponent, and bits <51:0> a 52-bit fraction.
The value (V) of a T_floating number is inferred from its constituent sign (S), exponent (E),
and fraction (F) fields as follows:
• If E=2047 and F<>0, then V is NaN, regardless of S.
• If E=2047 and F=0, then V = (–1)**S x Infinity.
• If 0 < E < 2047, then V = (–1)**S x 2**(E–1023) x (1.F).
• If E=0 and F<>0, then V = (–1)**S x 2**(–1022) x (0.F).
• If E=0 and F=0, then V = (–1)**S x 0 (zero).
Floating-point operations on T_floating numbers may take an arithmetic exception for a vari-
ety of reasons, including invalid operations, overflow, underflow, division by zero, and inexact
results.
Note:
Alpha implementations will impose a significant performance penalty when accessing
T_floating operands that are not naturally aligned. (A naturally aligned T_floating datum
has zero as the low-order three bits of its address.)
2.2.6.3 X_Floating
Support for 128-bit IEEE extended-precision (X_float) floating-point is initially provided
entirely through software. This section is included to preserve the intended consistency of
implementation with other IEEE floating-point data types, should the X_float data type be sup-
ported in future hardware.
An IEEE extended-precision, or X_floating, datum occupies 16 contiguous bytes in memory,
starting on an arbitrary byte boundary. The bits are labeled from right to left, 0 through 127, as
shown in Figure 2–15.
0
6362
S
32 31
Exp. Fraction Hi Fraction Lo :Fx
52 51