Compaq ECQD2KCTE Laptop User Manual


 
Waivers and Implementation-Dependent Functionality E–23
E.2.3 21264 Performance Monitoring
PALcode instructions control the 21264 on-chip performance counters. For OpenVMS Alpha,
the instruction is MTPR_PERFMON; for DIGITAL UNIX and Windows NT Alpha, the
instruction is wrperfmon.
The instruction arguments and results are described in the following sections. The scratch reg-
ister usage is operating system specific.
Two 20-bit on chip counters count events. Counters can be individually programmed, read, and
written.
Processes can be selectively monitored with the PME bit.
Profile monitoring for the 21264 is called aggregate mode profile monitoring because it pro-
vides an aggregate count.
E.2.3.1 Performance Monitor Interrupt Mechanism
The performance monitoring interrupt mechanism varies according to the particular operating
system.
For the OpenVMS Alpha Operating System
When a counter overflows and interrupt enabling conditions are correct, the counter causes an
interrupt to PALcode. The PALcode builds an appropriate stack frame. The PALcode then dis-
patches in the form of an exception (not in the form of an interrupt) to the operating system by
vectoring to the SCB performance monitor entry point through SCBB+650
(HWSCB$Q_PERF_MONITOR), at IPL 29, in kernel mode.
An interrupt is generated for each counter overflow. For each interrupt, the status of each
counter overflow is indicated by register R4:
R4 = 0 if performance counter 0 caused the interrupt
R4 = 1 if performance counter 1 caused the interrupt
When the interrupt is taken, the PC is saved on the stack frame as the old PC.
For the DIGITAL UNIX Operating System
When a counter overflows and interrupt enabling conditions are correct, the counter causes an
interrupt to PALcode. The PALcode builds an appropriate stack frame and dispatches to the
operating system by vectoring to the interrupt entry point entINT, at IPL 6, in kernel mode.
An interrupt is generated for each counter overflow. For each interrupt, registers a0..a2 are as
follows:
a0 = osfint$c_perf (4)
a1 = scb$v_perfmon (650)
a2 = 0 if performance counter 0 caused the interrupt
a2 = 1 if performance counter 1 caused the interrupt