Compaq ECQD2KCTE Laptop User Manual


 
Index–8
4–64
M
/M opcode qualifier, IEEE floating-point, 4–67
MAP_F function
, 2–4
MAP_S function
, 2–7
MAP_x operator
, 3–8
Mask byte instructions
, 4–57
MAX, defined for floating-point
, 4–65
MAXS(x,y) operator
, 3–8
MAXSB8 instruction
, 4–152
MAXSW4 instruction
, 4–152
MAXU(x,y) operator
, 3–8
MAXUB8 instruction
, 4–152
MAXUW4 instruction
, 4–152
MB (Memory barrier) instruction
, 4–142
compared with WMB
, 4–148
multiprocessors only
, 4–142
with DMA I/O, 5–22
with LDx_L/STx_C
, 4–14
with multiprocessor D-stream
, 5–22
with shared data structures, 5–9
See also IMB, WMB
MBZ (must be zero)
, 1–9
Memory access
aligned byte/word
, A–9
coherency of, 5–1
granularity of
, 5–2
width of
, 5–3
with WMB instruction, 4–147
Memory alignment, requirement for
, 5–2
Memory barrier instructions. See MB, IMB
(PALcode), and WMB instructions
Memory barriers
, 5–22
Memory format instructions
opcodes and format summarized
, C–1
Memory instruction format
, 3–11
Memory jump instruction format
, 3–12
Memory management
support in PALcode
, 6–2
Memory prefetch registers
defined
, 3–3
Memory-like behavior
, 5–3
MF_FPCR instruction
, 4–109
MIN, defined for floating-point
, 4–65
MINS(x,y) operator
, 3–8
MINSB8 instruction
, 4–152
MINSW4 instruction
, 4–152
MINU(x,y) operator
, 3–8
MINUB8 instruction
, 4–152
MINUW4 instruction
, 4–152
Miscellaneous instructions
, 4–132
Move instructions (conditional). See Conditional
move instructions
Move, register-to-register
, A–13
MSKBL instruction
, 4–57
MSKLH instruction
, 4–57
MSKLL instruction
, 4–57
MSKQL instruction
, 4–57
MSKWH instruction
, 4–57
MSKWL instruction
, 4–57
MT_FPCR instruction
, 4–109
synchronization requirement
, 4–82
MULF instruction
, 4–126
MULG instruction
, 4–126
MULL instruction
, 4–34
with MULQ
, 4–34
MULQ instruction
, 4–35
with MULL
, 4–34
with UMULH, 4–35
MULS instruction
, 4–127
MULT instruction
, 4–127
Multimedia instructions
, 4–151
Multiply instructions
multiply longword
, 4–34
multiply quadword
, 4–35
multiply unsigned quadward high, 4–36
See also Floating-point operate
Multiprocessor environment
cache coherency in
, 5–6
context switching
, 5–24
I-stream reliability, 5–23
MB and WMB with
, 5–22
no implied barriers
, 5–22
read/write ordering, 5–10
serialization requirements in
, 4–142
shared data
, 5–6, A–5