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Instruction Formats 3–3
3.1.5 Processor Cycle Counter (PCC) Register
The PCC register consists of two 32-bit fields. The low-order 32 bits (PCC<31:0>) are an
unsigned wrapping counter, PCC_CNT. The high-order 32 bits (PCC<63:32>), PCC_OFF, are
operating system dependent in their implementation.
PCC_CNT is the base clock register for measuring time intervals and is suitable for timing
intervals on the order of nanoseconds.
PCC_CNT increments once per N CPU cycles, where N is an implementation-specific integer
in the range 1..16. The cycle counter frequency is the number of times the processor cycle
counter gets incremented per second. The integer count wraps to 0 from a count of FFFF
FFFF
16
. The counter wraps no more frequently than 1.5 times the implementation’s interval
clock interrupt period (which is two thirds of the interval clock interrupt frequency), which
guarantees that an interrupt occurs before PCC _CNT overflows twice.
PCC_OFF need not contain a value related to time and could contain all zeros in a simple
implementation. However, if PCC_OFF is used to calculate a per-process or per-thread cycle
count, it must contain a value that, when added to PCC_CNT, returns the total PCC register
count for that process or thread, modulo 2**32.
Implementation Note:
OpenVMS Alpha and DIGITAL UNIX supply a per-process value in PCC_OFF.
PCC is required on all implementations. It is required for every processor, and each processor
on a multiprocessor system has its own private, independent PCC.
The PCC is read by the RPCC instruction. See Section 4.11.8.
3.1.6 Optional Registers
Some Alpha implementations may include optional memory prefetch or VAX compatibility
processor registers.
3.1.6.1 Memory Prefetch Registers
If the prefetch instructions FETCH and FETCH_M are implemented, an implementation will
include two sets of state prefetch registers used by those instructions. The use of these regis-
ters is described in Section 4.11. These registers are not directly accessible by software and are
listed for completeness.
3.1.6.2 VAX Compatibility Register
The VAX compatibility instructions RC and RS include the intr_flag register, as described in
Section 4.12.
3.2 Notation
The notation used to describe the operation of each instruction is given as a sequence of con-
trol and assignment statements in an ALGOL-like syntax.