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Instruction Descriptions 4–7
In the case of LDQ and LDL, the source operand is fetched from memory, sign-extended, and
written to register Ra.
In the case of LDWU and LDBU, the source operand is fetched from memory, zero-extended,
and written to register Ra.
In all cases, if the data is not naturally aligned, an alignment exception is generated.
Notes:
• The word or byte that the LDWU or LDBU instruction fetches from memory is placed
in the low (rightmost) word or byte of Ra, with the remaining 6 or 7 bytes set to zero.
• Accesses have byte granularity.
• For big-endian access with LDWU or LDBU, the word/byte remains in the rightmost
part of Ra, but the va sent to memory has the indicated bits inverted. See Operation sec-
tion, above.
• No sparse address space mechanisms are allowed with the LDWU and LDBU instruc-
tions.
Implementation Notes:
• The LDWU and LDBU instructions are supported in hardware on Alpha implementa-
tions for which the AMASK instruction returns bit 0 set. LDWU and LDBU are sup-
ported with software emulation in Alpha implementations for which AMASK does not
return bit 0 set. Software emulation of LDWU and LDBU is significantly slower than
hardware support.
• Depending on an address space region’s caching policy, implementations may read a
(partial) cache block in order to do word/byte stores. This may only be done in regions
that have memory-like behavior.
• Implementations are expected to provide sufficient low-order address bits and
length-of-access information to devices on I/O buses. But, strictly speaking, this is out-
side the scope of architecture.