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Instruction Descriptions 4–11
If two LDx_L instructions execute with no intervening STx_C, the second one
overwrites the state of the first one. If two STx_C instructions execute with no
intervening LDx_L, the second one always fails because the first clears lock_flag.
• Software will not emulate unaligned LDx_L instructions.
• If the virtual and physical addresses for a LDx_L and STx_C sequence are not within
the same naturally aligned 16-byte sections of virtual and physical memory, that
sequence may always fail, or may succeed despite another processor’s store to the lock
range; hence, no useful program should do this.
• If any other memory access (ECB, LDx, LDQ_U, STx, STQ_U, WH64) is executed on
the given processor between the LDx_L and the STx_C, the sequence above may
always fail on some implementations; hence, no useful program should do this.
• If a branch is taken between the LDx_L and the STx_C, the sequence above may
always fail on some implementations; hence, no useful program should do this.
(CMOVxx may be used to avoid branching.)
• If a subsetted instruction (for example, floating-point) is executed between the LDx_L
and the STx_C, the sequence above may always fail on some implementations because
of the Illegal Instruction Trap; hence, no useful program should do this.
• If an instruction with an unused function code is executed between the LDx_L and the
STx_C, the sequence above may always fail on some implementations because an
instruction with an unused function code is UNPREDICTABLE.
• If a large number of instructions are executed between the LDx_L and the STx_C, the
sequence above may always fail on some implementations because of a timer interrupt
always clearing the lock_flag before the sequence completes; hence, no useful program
should do this.
• Hardware implementations are encouraged to lock no more than 128 bytes. Software
implementations are encouraged to separate locked locations by at least 128 bytes from
other locations that could potentially be written by another processor while the first
location is locked.
• Execution of a WH64 instruction on processor A to a region within the lock range of
processor B, where the execution of the WH64 changes the contents of memory, causes
the lock_flag on processor B to be cleared. If the WH64 does not change the contents of
memory on processor B, it need not clear the lock_flag.
Implementation Notes:
Implementations that impede the mobility of a cache block on LDx_L, such as that which
may occur in a Read for Ownership cache coherency protocol, may release the cache block
and make the subsequent STx_C fail if a branch-taken or memory instruction is executed
on that processor.
All implementations should guarantee that at least 40 non-subsetted operate instructions
can be executed between timer interrupts.