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4–12 Alpha Architecture Handbook
4.2.5 Store Integer Register Data into Memory Conditional
Format:
Operation:
va ← {Rbv + SEXT(disp)}
CASE
big_endian_data: va’ ← va XOR 000
2
! STQ_C
big_endian_data: va’ ← va XOR 100
2
! STL_C
little_endian_data: va’ ← va ! STL_C
ENDCASE
IF lock_flag EQ 1 THEN
(va’)<31:0> ← Rav<31:0> ! STL_C
(va’) ← Rav ! STQ_C
Ra ← lock_flag
lock_flag ← 0
Exceptions:
Instruction mnemonics:
Qualifiers:
Description:
The virtual address is computed by adding register Rb to the sign-extended 16-bit displace-
ment. For a big-endian longword access, va<2> (bit 2 of the virtual address) is inverted, and
any memory management fault is reported for va (not va’).
If the lock_flag is set and the address meets the following constraints relative to the address
specified by the preceding LDx_L instruction, the Ra operand is written to memory at this
address. If the address meets the following constraints but the lock_flag is not set, a zero is
returned in Ra and no write to memory occurs. The constraints are:
STx_C Ra.mx,disp.ab(Rb.ab)
!Memory format
Access Violation
Fault on Write
Alignment
Translation Not Valid
STL_C Store Longword from Register to Memory Conditional
STQ_C Store Quadword from Register to Memory Conditional
None