Compaq ECQD2KCTE Laptop User Manual


 
4–16 Alpha Architecture Handbook
The Ra operand is written to memory at this address. If the data is not naturally aligned, an
alignment exception is generated.
Notes:
The word or byte that the STB or STW instruction stores to memory comes from the
low (rightmost) byte or word of Ra.
Accesses have byte granularity.
For big-endian access with STB or STW, the byte/word remains in the rightmost part of
Ra, but the va sent to memory has the indicated bits inverted. See Operation section,
above.
No sparse address space mechanisms are allowed with the STB and STW instructions.
Implementation Notes:
The STB and STW instructions are supported in hardware on Alpha implementations
for which the AMASK instruction returns bit 0 set. STB and STW are supported with
software emulation in Alpha implementations for which AMASK does not return bit 0
set. Software emulation of STB and STW is significantly slower than hardware support.
Depending on an address space region’s caching policy, implementations may read a
(partial) cache block in order to do byte/word stores. This may only be done in regions
that have memory-like behavior.
Implementations are expected to provide sufficient low-order address bits and
length-of-access information to devices on I/O buses. But, strictly speaking, this is out-
side the scope of architecture.