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CY62147EV30 MoBL
®
4-Mbit (256K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-05440 Rev. *G Revised March 31, 2009
Features
■
Very high speed: 45 ns
■
Temperature ranges
❐
Industrial: –40°C to +85°C
❐
Automotive-A: –40°C to +85°C
❐
Automotive-E: –40°C to +125°C
■
Wide voltage range: 2.20V to 3.60V
■
Pin compatible with CY62147DV30
■
Ultra low standby power
❐
Typical standby current: 1 μA
❐
Maximum standby current: 7 μA (Industrial)
■
Ultra low active power
❐
Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE
[1]
and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in Pb-free 48-ball VFBGA (single/dual CE option) and
44-pin TSOPII packages
■
Byte power down feature
Functional Description
The CY62147EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life™ (MoBL
®
) in portable appli-
cations such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE
HIGH or both BLE and BHE are
HIGH). The input and output pins (IO
0
through IO
15
) are placed
in a high impedance state when:
■
Deselected (CE HIGH)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE
, BLE HIGH)
■
Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE
) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO
0
through IO
7
) is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE
) is LOW, then data from IO pins (IO
8
through IO
15
)
is written into the location specified on the address pins (A
0
through A
17
).
To read from the device, take Chip Enable (CE
)
and Output
Enable (OE
) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE
) is LOW, then data from the memory
location specified by the address pins appear on IO
0
to IO
7
. If
Byte High Enable (BHE
) is LOW, then data from memory
appears on IO
8
to IO
15
. See the Truth Table on page 9 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
256K x 16
RAM Array
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO
8
–IO
15
CE
[1]
WE
BHE
A
16
A
0
A
1
A
9
A
10
BLE
A
17
BHE
BLE
CE
POWER DOWN
CIRCUIT
Logic Block Diagram
Note
1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE
refers to the internal logical combination of CE
1
and
CE
2
such that when CE
1
is LOW and CE
2
is HIGH, CE is LOW. For all other cases CE is HIGH.
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