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Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document Number: 001-08353 Rev. *C Revised November 6, 2008
CY7C1024DV33
3-Mbit (128K X 24) Static RAM
Features
■
High speed
❐
t
AA
= 10 ns
■
Low active power
❐
I
CC
= 175 mA at 10 ns
■
Low CMOS standby power
❐
I
SB2
= 25 mA
■
Operating voltages of 3.3 ± 0.3V
■
2.0V data retention
■
Automatic power down when deselected
■
TTL compatible inputs and outputs
■
Easy memory expansion with CE
1
, CE
2
, and CE
3
features
■
Available in Pb-free standard 119-ball PBGA
Functional Description
The CY7C1024DV33 is a high performance CMOS static RAM
organized as 128K words by 24 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
To write to the device, enable the chip (CE
1
LOW, CE
2
HIGH,
and CE
3
LOW), while forcing the Write Enable (WE) input LOW.
To read from the device, enable the chip by taking CE
1
LOW, CE
2
HIGH, and CE
3
LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE
) HIGH. See the Truth Table on page
7 for a complete description of Read and Write modes.
The 24 I/O pins (I/O
0
to I/O
23
) are placed in a high impedance
state when the device is deselected (CE
1
HIGH, CE
2
LOW, or
CE
3
HIGH) or when the output enable (OE) is HIGH during a
write operation. (CE
1
LOW, CE
2
HIGH, CE
3
LOW, and WE
LOW).
Logic Block Diagram
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
128K x 24
ARRAY
I/O
0
– I/O
23
OE
CE
1
, CE
2
, CE
3
WE
CONTROL LOGIC
A
(9:0)
A
(16:10)
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