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8 RS/6000 7025 Model F80 Technical Overview
2- and 4- Way SMP
A 2-way SMP configuration is provided by a processor board
consisting of a pair of RS64 III processors operating at 450 MHz and a
memory controller. Expansion to 4-way SMP is provided by interfacing
an additional processor board consisting of a pair of RS64 III
processors operating at 450 MHz. However, the upgrade from 2-way to
4-way SMP is offered as a book swap, since the addition of the
processor card on the processor book is too delicate for field handling.
6-Way SMP
A 6-way SMP configuration uses two processor boards which are
interfaced to each other. One processor board consists of a pair of
RS64 III processors operating at 500 MHz and a memory controller.
The other processor board consists of four RS64 III processors
operating at 500 MHz. Upgrades from a 2- or 4-way SMP to a 6-way
SMP are offered as a book swap.
Memory Controller
A single custom chip provides the function of the memory controller and the I/O
hub in the Model F80. The controller chip provides interfaces to processors,
memory, and the I/O subsystem.
The RS64 III processors on the processor boards are connected to the memory
controller through the PowerPC 6xx bus. The controller chip is a part of the first
processor board. The memory controller provides a single 6xx bus interface in a
single processor configuration. For 2-way SMP configurations, the controller
provides a 6xx bus interface to the pair of RS64 III processors present in the
same board. The memory controller provides another 6xx bus interface for CPU
expansion using an additional processor board. The 4- and 6-way SMP
configurations consists of a total of two processor boards which uses the two 6xx
bus interfaces provided by the memory controller installed together in a book.
In the Model F80, the 6xx bus is a 16-byte wide bus and the operating clock rate
of the bus depends upon the processor clock speed. The 6xx bus operates at a
clock rate of 150 MHz, for a processor clock speed of 450 MHz. And for a
processor clock speed of 500 MHz, the 6xx bus operates at a clock rate of 125
MHz.
Memory Subsystem
The memory controller provides two memory bus interfaces and provides the
reliability functions of ECC as well as memory scrubbing. Memory scrubbing
provides a built-in hardware function that is designed to perform continuous
background reads of data from memory, checking for correctable errors. The
memory configuration for a single processor configuration and 2-, 4-, or 6-way
configurations is explained as follows:
• In a single processor configuration, the on-board memory, consisting of eight
DIMM slots, is interfaced to one of the two memory interfaces in the controller.
The other interface is used by a separate riser memory card. The riser
memory card provides 16 DIMM slots. While the DIMM slots in the on-board
memory are populated in pairs, the slots in the riser memory card are
populated in quads. The minimum configuration requires a pair of DIMMs in
the on-board memory. Once the on-board memory slots are filled and more
memory capacity is desired, the DIMMs are moved to the riser memory card
and the next increment is made as a quad. The single processor configuration