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ADE-6050 User’s Manual
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4.2.3 Advanced Chipset Features
4.2.3.1 DRAM Timing Selectable
Select the operating system that is selecting DRAM timing, so select SPD for setting
SDRAM timing by SPD.
The Choice: Manual, By SPD.
4.2.3.2 CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing.
4.2.3.3 DRAM RAS# to CAS# Delay
The system board designer should set the values in this field, depending on the DRAM
installed. Do not change the values in this field unless you change specifications of the
installed DRAM or the installed CPU. This field is locked when “DRAM Timing Selectable” is
set to “By SPD” and is automatically determined by the system.
The choice: Auto, 5, 4, 3, 2.