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The pacer trigger can control the sampling rate very precisely. So the converted
data can be used to reconstruct the waveform of the analog input signal. In pacer trigger
mode, the pacer timer will periodically generate trigger signals to the A/D converter. This
converted data can be transfer to the CPU by polling or interrupt or DMA transfer method.
The software driver provides three polling or interrupt-transfer methods. The polling
subroutine, A8111_AD_PollingVar() or A822_AD_PollingArray(), sets the A/D mode
control register to 0x01. This control word means software trigger and polling transfer. The
interrupt subroutine, A822_AD_INT_START(…), sets the A/D mode control mode register
to ox06. This control word means pacer trigger and interrupt transfer. The interrupt
subroutine, A822_AD_DMA_START(…), sets the A/D mode control register to 0x06 This
control word means pacer trigger and DMA transfer.
2.4.9 A/D Software Trigger Control Register
(WRITE) Base+C : A/D Software Trigger Control Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X X X X X X X X
X=don‘t care, XXXXXXXX=any 8 bits data is validate
The A/D converter can be triggered by software trigger or pacer trigger. Detailed
information is given in sec.2.4.8 and 2.7. Writing any value to address BASE+C will
generate a trigger pulse to the A/D converter and initiate an A/D conversion operation. The
address BASE+5 offers a ready bit to indicate that an A/D conversion is complete.
The software driver uses this control word to detect the OME-A-8111 hardware board.
The software initiates a software trigger and checks the ready bit. If the ready bit cannot
clear to zero in a fixed time, the software driver will return an error message. If there is an
error in the I/O BASE address setting, the ready bit will not be cleared to zero. The software
driver, A8111_CheckAddress(), uses this method to detect the status of the I/O BASE
address setting.
OME-A-8111 Hardware Manual (ver.1.1, Jul/2003) 17