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Philips Semiconductors
User’s Manual - Preliminary -
P89LPC906/907/908
UART
2003 Dec 8 66
DOUBLE BUFFERING
The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character
is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two
characters, provided the next character is written between the start bit and the stop bit of the previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e. SSTAT.7 = 0), the UART is compatible with the conventional 80C51
UART. If enabled, the UART allows writing to SBUF while the previous data is being shifted out.
DOUBLE BUFFERING IN DIFFERENT MODES
Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).
TRANSMIT INTERRUPTS WITH DOUBLE BUFFERING ENABLED (MODES 1, 2 AND 3)
Unlike the conventional UART, when double buffering is enabled, the Tx interrupt is generated when the double buffer is ready
to receive new data. The following occurs during a transmission (assuming eight data bits):
1. The double buffer is empty initially.
2. The CPU writes to SBUF.
3. The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately.
4. If there is more data, go to 6, else continue on 5.
5. If there is no more data, then:
- If DBISEL is ’0’, no more interrupts will occur.
- If DBISEL is ’1’ and INTLO is ’0’, a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter
(which is also the last data).
- If DBISEL is ’1’ and INTLO is ’1’, a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter (which
is also the last data).
6. If there is more data, the CPU writes to SBUF again. Then:
- If INTLO is ’0’, the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently
in the shifter.
- If INTLO is ’1’, the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the
shifter.
Go to 3.
Note that if DBISEL is ’1’ and the CPU is writing to SBUF when the STOP bit of the last data is shifted out, there can be an
uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following.