Philips P89LPC907 Computer Monitor User Manual


 
Philips Semiconductors
User’s Manual - Preliminary -
P89LPC906/907/908
CLOCKS
2003 Dec 8 28
LOW POWER SELECT (P89LPC906)
The P89LPC906 is designed to run at 12MHz (CCLK) maximum. However, if CCLK is 8MHz or slower, the CLKLP SFR bit
(AUXR1.7) can be set to a ’1’ to lower the power consumption further. On any reset, CLKLP is ’0’ allowing highest performance.
This bit can then be set in software if CCLK is running at 8MHz or slower.
Figure 2-3: Block Diagram of Oscillator Control - P89LPC906
RTC
CPU
High freq.
Med freq.
Low freq.
Watchdog
Oscillator
RC Oscillator
XTAL1
XTAL2
/2
DIVM
WDT
(7.3728MHz)
(400KHz)
CCLK
PCLK
Timer 0 & 1
OSC
CLK
Oscillator
Clock
CPU
Clock
FOSC2:0
RTCS1:0