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PM8385
Released
QuadPHY RT
PMC-2030741 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., © Copyright PMC-Sierra, Inc. 2003.
Issue 2 AND FOR ITS CUSTOMERS’ INTERNAL USE All rights reserved.
4-Port Gigabit Ethernet and 1/2G Fibre Channel Repeater or Retimer
GENERAL
• Supports four physical interfaces for
Gigabit Ethernet at 1.25 Gbit/s per
IEEE 802.3z or Fibre Channel physical
interfaces at 1.0625 or 2.125 Gbit/s per
Fibre Channel Physical Interface (FC-
PI) for repeating or retiming
applications.
• Backplane repeating/retiming signal
integrity features enable standards
compliance, link extension and robust
gigabit-serial operation in the hostile
backplane environment.
• Provides direct connection to high-
speed serial backplanes, coax
stacking cables, or optical / copper
Small Form Factor Pluggable (SFP)
modules.
• Provides non-blocking cross-bar for
protection switching and data bi-cast,
multi-cast or broadcast.
• Fast high-speed serial lock times and
low device latency.
• Rate detection/auto-selection between
1G and 2G Fibre Channel.
• Extensive per port backplane
monitoring for loss of signal, error rates,
and link level violations.
• Supports single-ended or differential
125 MHz reference clock for Gigabit
Ethernet, or 106.25 MHz reference
clock for Fibre Channel applications.
HIGH-SPEED INTERFACE
• High-speed outputs with selectable
output amplitude and programmable
pre-emphasis per port to counteract
dielectric losses and allow maximum
reach on printed circuit boards and
cables.
• Programmable receive input
equalization provides robust data
recovery of highly degraded input
signals.
• Minimal board footprint and exceptional
signal integrity achieved:
• No external components are required
to interface the high-speed signals
due to internal AC coupling.
• Programmable receive input
termination of 100 ohm or 150 ohm
differential.
• Programmable output impedance of
100 ohm or 150 ohm differential.
TEST AND CONTROL
• Digital loss of link (DLOL) detect pin
provides status output for monitoring
individual or multiple links.
• DLOL and optional interrupt pin can be
programmed to indicate:
• Analog loss of signal.
• Excessive 8B/10B code and disparity
violations.
• Fibre Channel comma density.
• Loss of synchronization to detect
Gigabit Ethernet or Fibre Channel
framing errors.
• Internal packet generator and
comparator features simplify backplane
and jitter testing via:
• Programmable pattern (can be used
with GE high, low and mixed
frequency tests).
Cross-bar
Pattern
Generator/
Comparator
CDRU
SERDES/
Reclocker
Rx
Retimer/
Monitor
Tx
Control
10
10
SERDES/
Reclocker
Rx
Retimer/
Monitor
Tx
Control
10
10
SERDES/
Reclocker
Rx
Retimer/
Monitor
Tx
Control
10
10
SERDES/
Reclocker
Rx
Retimer/
Monitor
Tx
Control
10
10
RDIP[0]
RDIN[0]
2
2
TDOP[0]
TDON[0]
RDIP[1]
RDIN[1]
2
2
TDOP[1]
TDON1]
RDIP[2]
RDIN[2]
2
2
TDOP[2]
TDON[2]
RDIP[3]
RDIN[3]
2
2
TDOP[3]
TDON[3]
Impedance
Control
Two Wire
Interface
Control Block
PREEMPH[1:0]
R
E
C
E
Q
U
A
L
I
Z
E
[
1
:
0
]
DLOLBYP_MASK
RET_MODE
FC_GE_RET_SEL
HALF_RATE
AUTO_RATE_SEL
TX100/
150[3:0]
RX100/
150[3:0]
TWISEL
MDIO_SDA
MDC_SCL
DVPRTAD[4:0]
RESETB
REFCLK_S
CLK_SEL
REFCLK_N
REFCLK_P
RPRES
EXTCAP
JTAG
TDO
TDI
TMS
TCK
TRSTB
DLOLB
PORT_DLOLB[3:0]
INTRB
PORT_2G_RATE[3:0]
B
LOCK DIAGRAM