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J2
Pin Circuit Net Name Device
Pin
Pin Circuit Net Name Device
Pin
1 D7 31 2 D6 32
3 D5 33 4 D4 34
5 D3_LED3 35 6 UC_VCC -
7 D2_LED2 37 8 D1_LED1 38
9 GROUND 39 10 D0_LED0 40
11 CS1n_CRx0 41 12 CTx0 42
13 A19_CAN_STBn 43 14 A18_IRQ2 44
15 A17_IRQ1_SDA 45 16 A16_IRQ0_SCL 46
17 M2_TRISTn 47 18 UC_VCC -
19 UD_CAN_EN 49 20 GROUND -
Table 9-2: J2
J3
Pin Circuit Net Name Device
Pin
Pin Circuit Net Name Device
Pin
1 IO7 51 2 A10_IO6 52
3 A9_IO5 53 4 A8_IO4 54
5 A8_ADTRGn_IO3 55 6 A6_IO2 56
7 UC_VCC - 8 TXD2_IO1 58
9 NC - 10 WRLn_WRn_RXD2_IO0 60
11 SCK2 61 12 RDn 62
13 A5_IRQ3_CAN_ERRn 63 14 GROUND -
15 A4_PTTX 65 16 A3_PTRX 66
17 A2_SCK0 67 18 A1_TXD0 68
19 A0_RXD0 69 20 RESn 70
21 CON_XTAL 71 22 CON_EXTAL 72
23 NMI 73 24 FWE 74
25 NC - 26 ASEMD0n 76
27 MD1 77 28 MD0 78
29 CON_AVSS 79 30 AN15 80
Table 9-3: J3
25