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S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET
6-37
DI — Disable Interrupts
DI
Operation: SYM (0) ← 0
Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all
interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,
but the CPU will not service them while interrupt processing is disabled.
Flags: No flags are affected.
Format:
Bytes Cycles Opcode
(Hex)
opc 1 4 8F
Example: Given: SYM = 01H:
DI
If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the
register and clears SYM.0 to "0", disabling interrupt processing.
Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.